In recent years, in order to improve flexibility of processing, there has increased an LSI (Large Scale Integration) in which a dedicated coprocessor is connected to a built-in processor core to perform signal processing.
In the LSI in which the coprocessor core and the processor are connected to each other, a coprocessor 20 and a data memory 30 can be directly connected to each other as shown in FIG. 5. The coprocessor 20 directly performs read and write of data with respect to the data memory 30. As a result of this, data traffic of a processor core 10 is reduced, and performance can be improved.
For example, Patent Literature 1 discloses a configuration in which data is directly transferred between a coprocessor and a data memory.
For example, the following methods are included in techniques to generate an address required for data exchange between the coprocessor and the data memory etc.
(1-1) A method in which a data transfer circuit in the coprocessor automatically generates the address
(1-2) A method for directly embedding an address value in an instruction (hereinafter referred to as a coprocessor instruction) issued to the coprocessor
(1-3) A method for embedding an update parameter of the address value in the coprocessor instruction
(1-4) A method for appropriately supplying the address from a processor core
Among the above-described methods, “(1-1) The method in which the data transfer circuit in the coprocessor automatically generates the address” has a high processing efficiency, and has a high efficiency of a control program. Hereinafter, a coprocessor in an LSI in which the method is employed will be described with reference to FIG. 6. A data transfer circuit 23 in the coprocessor automatically generates an address using a data transfer parameter 231. The data transfer circuit 23 reads data from the data memory 30 using the generated address. The data transfer circuit 23 writes the read data in an arithmetic unit 22 through a data input FIFO (First In First Out) 25. The arithmetic unit 22 performs arithmetic operation using the input data, and writes an arithmetic result in a data output FIFO 26 and the data transfer circuit 23.
When an address is automatically generated in the data transfer circuit 23, a parameter for address generation (a data transfer parameter) is set to the data transfer circuit 23, and after that, a series of coprocessor instructions are issued. The data transfer circuit 23 generates the address using the data transfer parameter 231 in synchronization with the issue of the coprocessor instructions. After address generation, the data transfer circuit 23 performs data write or data read in or from the data memory 30. Each configuration of the LSI is implemented so that the above-mentioned operation is performed.
When the data transfer circuit 23 in the coprocessor 20 generates the address, a plurality of data transfer parameter settings may be required for the data transfer circuit 23 depending on complexity of the address to be generated. When the address to be generated does not vary, and it is simple, setting of the data transfer parameter may just be performed only once. However, for example, when an address is irregularly changed in the middle of execution of the coprocessor instruction, resetting of the data transfer parameter is required during execution of the coprocessor instruction.
For example, the following methods are included in methods for resetting a data transfer parameter.
(2-1) A method for repeatedly execute each processing included in a coprocessor instruction, repeatedly halting processing in a timing required for address change, and setting a data transfer parameter.
(2-2) A method for generating interrupt to a coprocessor in a timing of changing an address, and setting a data transfer parameter in interrupt processing
The above-mentioned method of (2-1) will be described with reference to FIG. 7. As shown in FIG. 7, a coprocessor repeatedly executes a coprocessor instruction (loop processing in S22). In the timing when an address is changed, a data transfer parameter is set from outside (S21). When this method is employed, it is necessary to generate a control program in consideration of the timing of address change. Therefore, there is such a problem that when the address is irregularly changed in the middle of execution of the coprocessor instruction, the control program becomes complicated.
Subsequently, the method of (2-2) will be described with reference to FIGS. 8 and 9. First, there will be described general operation in a case where interrupt processing is executed to a coprocessor with reference to FIG. 8.
In the case where interrupt processing to the coprocessor is performed during execution of a coprocessor instruction, when the interrupt processing is executed before the end of the coprocessor instruction, problems, such as resource mismatch inside the coprocessor, may occur. Therefore, interrupt processing is suspended until the coprocessor instruction is ended as shown in FIG. 8.
For example, Patent Literature 2 discloses a technology in which when external interrupt is generated during processing of a vector instruction, processing of the external interrupt is suspended until the processing of the vector instruction is ended. As a result of this, an arithmetic result of the vector instruction is prevented from being an illegal value.
Subsequently, the method of (2-2) will be described with reference to FIG. 9. As shown in FIG. 9, interrupt is generated at a timing when a parameter for address generation needs to be reset (S43). As a result of this, a control program of an LSI can be simplified.
However, this method causes such a problem that deadlock may occur. The problem will be described with reference to FIG. 10. As described with reference to FIG. 8, in order to avoid resource mismatch, interrupt processing is generally executed after the program waits until the end of the coprocessor instruction. Therefore, interrupt processing is not executed until the end of the coprocessor instruction (S51). Meanwhile, since interrupt processing is not executed, parameter setting of a data transfer circuit is not executed (S52). Since the parameter setting is not executed, data acquisition (access to a data memory) by the coprocessor instruction being executed cannot be executed (S53). Therefore, the coprocessor instruction is not ended (S54). As described above, a deadlock state occurs.
Patent Literature 3 discloses a technology to eliminate deadlock due to the program continuing to wait until data is held in a buffer in performing stream data. In the technology, when timeout occurs, deadlock is avoided by inserting dummy data in an FIFO buffer that holds the stream data. Namely, a configuration is disclosed in which processing is forcibly executed for each certain time.